Analogue Fault Simulation using Device Latency

In the case of digital circuits, the possible defects in a circuit may be modelled by faults such as the singlestuck fault model and bridging faults. Thus a very large numbe of possible defects may be reduced to a relatively small number of faults. In digital fault simulation, a number of copies of the circuit are made, each of which contains exactly one fault, together with the fault-free circuit. In the simplest case, each faulty circuit is simulated using test vectors as excitations and the results of each simulation compared with those of the fault-free circuit. If a circuit contains n nodes, there are 2n possible stuck faults (each node may be stuck at 1 or at 0), and therefore 2n + 1 simulations are required. Some faults can be considered equivalent and the number of simulations reduced, but in general, the number of simulations soon becomes prohibitive. Consequently, various fault simulation techniques have been developed to reduce the simulation time1. Parallel fault simulation, as its name suggests, simulates the fault-free circuit and a number of faulty circuits simultaneously, thereby simplifying the simulation process. Deductive and concurrent fault simulation work on the principle that, for much of the time, the differences between a faulty circuit and the fault-free circuit are relatively small. In logic simulation, node values are represented typically by the set {0; 1; Z ; X}, thus any differences may be stored by at most 2 bits. By simulating and storing only the differences, the time taken to simulate all 2n − 1 circuits is much reduced.